CMPE100/L
Logic Design

Welcome to CMPE100

Homework Assignments

• Homework 1:
• Homework 2:
• Homework 3:
• Homework 4:
• Homework 5:
• Homework 6: due Friday December 7 in Canvas at 10pm PDT.
(Solutions will be available in Canvas under Files)

Labs

Lab 8
Demo due: Thursday 12/6 end of your section
Write-Up due: Wednesday 12/12 11:55pm
Last day to submit Write-Up: Thursday 12/13 11:55pm
(with late penalty)
• Lab 7
  Demo due: Thursday 11/29 end of your section
  Two early demo bonuses are available for Lab 7, click here for details
  Write-Up due: Friday 12/7 11:55pm
  Last day to submit Write-Up: Tuesday 12/12 11:55pm
  (with late penalty)
• Lab 6
  Demo due: Thursday 11/15 end of your section
  Write-Up due: Friday 11/23 11:55pm
• Lab 5
  Demo due: Thursday 11/8 end of your section
  Write-Up due: Friday 11/16 11:55pm
• Lab 4
• Lab 3
• Lab 2
• Lab 1

Course Resources

• Slides
• Lab Write-Ups
• Your Engineering Notebook
• Lab resource page
(includes directions for installing lab software on your Windows or Linux PC)
• Lab policies (a must read!)
• Topic, homework and reading schedule
• Text: Fundamentals of Digital Logic with Verilog Design by Stephen Brown and Zvonko Vranesic.
  First or Second or Third Edition
  McGraw-Hill 2013. ISBN-13: 978-0073380544 or ISBN-10: 0073380547 (these are the ISBNs for the third edition)
  

  There are several options for acquiring the text:
  But make sure the version you get says Verilog and not VHDL.

  1. Buy a new or used version of any edition from ??? for ???
  2. Buy the custom version of the text (ISBN:9781308394329) from the UCSC bookstore for $107.50.
     This is a new softcover black and white version of the text with only the chapters that will be covered.
  3. Rent the e-book version of the custom text through the bookstore.
  4. Buy the e-book version of this text from McGraw-Hill.

Course Information

• Lecture: MWF 9:20-10:25am Kresge 327
• Lab: Baskin Engineering 104.
  • Section 1 TuTh 9:50-11:40am
  • Section 2 TuTh 11:40-1:30pm
  • Section 3 TuTh 1:30-3:20pm
  • Section 4 TuTh 3:20-5:10pm
  You must attend at least the first meeting of your section each week and you will probably need to attend the second as well.
  You may work in the lab at other times (and you will need to!).
  Installing the Vivado Webpack on your windows or linux computer will make you less dependent on the lab. If you bring your laptop to the lab we can help you install it. If you have a Mac you can run Vivado by installing Windows using Bootcamp or a Virtual environment such as VMWare.

Staff:

• Instructor: Max Dunne
  e-mail: mdunne followed by @soe.ucsc.edu
  Office Hours: Fridays 11AM-12PM
  E2-329
• TAs:
  • Hany Fahmy e-mail: hfahmy followed by @ucsc.edu
  • Erik Jung e-mail: eajung followed by @ucsc.edu
• Lab Tutors:
  • Hunter Coffman e-mail: hcoffman followed by @ucsc.edu
  • Harley Berman e-mail: haaberma followed by @ucsc.edu
  • Olyad Kebede e-mail: okebede followed by @ucsc.edu
  • Thomas Nijssen e-mail: tnijssen followed by @ucsc.edu
  • Christopher Cheney e-mail: crcheney followed by @ucsc.edu

• MSI Learning Assistant:
  TBD

• Grading
• Pre-requisite: CMPE12/L
• Requesting academic accommodations

Other Information

• Academic Integrity
• SOE home page
• FPGA FAQ
• Murphy's Law
• Unacceptable proof techniques
• Direction of current flow (the holes have it!)
• Pictures of MOS transistors (Scroll down to about the middle of the page)
• Lego Logic
• Off-topic but an example of a thorough report: An engineer's guide to cats

Portions of the CMPE100 Web may be reprinted or adapted for academic nonprofit purposes, providing the source is accurately quoted and duly credited.