CMPE100 Slides -- Fall 18
Verilog for State Machine logic of TAPS Bike Counter (pdf)
State Minimization Slides (pdf)
Delay Slides (pdf)
Flip-Flop Slides (pdf)
SROM interface example slides (or how to communicate asynchronously) (pdf)
Tri-State Buses (pdf)
FPGA Slides (pdf)
Two-level logic minimization: Quine-McCluskey(pdf)
The CMPE100 Web:
Copyright 2018; Department of Computer Engineering,
University of California, Santa Cruz.
Comments to:
martine@cse.ucsc.edu