CMPE100/L
Logic Design

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Local time: Sat Apr 27 16:41:41 2024 PDT )

Discussion: Piazza cmpe100/L forum

Homework Assignments

• Homework 6: due Friday March 17 in Canvas at 10pm PST.
• Homework 5: due Wednesday March 1 in Canvas at 10pm PST.
• Homework 4: due Saturday February 18 in Canvas at 10pm PST.
• Homework 3: due Wednesday February 1 in Canvas at 10pm PST.
• Homework 2: due Friday January 27 in Canvas at 10pm PST.
• Homework 1: due Friday January 20 in Canvas at 10pm PST.
(Solutions will be available in Canvas under Files)

Labs

• Lab 8
  Demo due: Thursday 3/16 end of your section
  Write-Up due: Tuesday 3/21 11:55pm
  Last day to submit Write-Up: Thursday 3/23 11:55pm
  (with late penalty)
• Lab 7
  Demo due: Thursday 3/9 end of your section
  Write-Up due: Friday 3/17 11:55pm
  Last day to submit Write-Up: Wednesday 3/2211:55pm
  (with late penalty)
• Lab 6
• Lab 5
• Lab 4
• Lab 3
• Lab 2
• Lab 1

Course Resources

• Slides
• Lab Write-Ups
• Your Engineering Notebook
• Lab resource page
(includes directions for installing lab software on your Windows or Linux PC)
• Lab policies (a must read!)
• Topic, homework and reading schedule
• Text: Fundamentals of Digital Logic with Verilog Design by Stephen Brown and Zvonko Vranesic.
  First or Second or Third Edition
  McGraw-Hill 2013. ISBN-13: 978-0073380544 or ISBN-10: 0073380547 (these are the ISBNs for the third edition)
  

  There are several options for acquiring the text:
  But make sure the version you get says Verilog and not VHDL.

  1. Buy a new or used version of any edition from ??? for ???
  2. Buy the custom version of the text (ISBN:9781308394329) from the UCSC bookstore for $99.95.
     This is a new softcover black and white version of the text with only the chapters that will be covered.
  3. Rent the e-book version of the custom text through the bookstore.
  4. Buy the e-book version of this text from McGraw-Hill.

Course Information

• Lecture: MWF 1:20-2:25pm Kresge Classroom 321
• Lab: Baskin Engineering 104.
  • Section 1 TuTh 10:00-11:50am
  • Section 2 TuTh 12:00-1:50pm
  • Section 3 TuTh 2:00-3:50pm
  • Section 4 TuTh 4:00-5:50pm
  • Section 5 TuTh 6:00-7:50pm
  You must attend at least the first meeting of your section each week and you will probably need to attend the second as well.
  You may work in the lab at other times (and you will need to!).
  Installing the Vivado Webpack on your windows or linux computer will make you less dependent on the lab. If you bring your laptop to the lab we can help you install it. If you have a Mac you can run Vivado by installing Windows using Bootcamp or a Virtual environment such as VMWare.
• MSI Sections:
  • Monday 9:20AM - 10:20AM at ARCenter 116
  • Wednesday 4:00PM - 5:00PM at ARCenter 116
  • Wednesday 5:20PM - 6:20PM at ARCenter 221
  • Friday 2:40PM - 3:40 PM at ARCenter116

• Staff:
• Instructor: Martine Schlag
  e-mail: martine followed by @soe.ucsc.edu
  Office Hours: Tuesday 1:00-2:00pm and Friday 11:00am-noon
  E2 219 (northwest corner), (831)459-3243
• TAs:
  • Dawn Hustig-Schultz e-mail: dhustigs followed by @ucsc.edu
  • Blake Skinner e-mail: hskinner followed by @ucsc.edu
  • Joseph Grant e-mail: jdgrant followed by @ucsc.edu
• Lab Tutors:
  • Roger Berman e-mail: raberman followed by @ucsc.edu
  • Harsh Bhakta e-mail: habhakta followed by @ucsc.edu
  • Tyler Clinkaberry e-mail: tclinkab followed by @ucsc.edu
  • Cole Faust e-mail: cfaust followed by @ucsc.edu
  • Madeline Schade e-mail: mcschade followed by @ucsc.edu
• MSI Learning Assistant:
  • Jason Ting e-mail: jting2 followed by @ucsc.edu

• Grading
• Pre-requisite: CMPE12/L
• Requesting academic accommodations

Other Information

• SOE home page
• FPGA FAQ
• Murphy's Law
• Unacceptable proof techniques
• Direction of current flow (the holes have it!)
• Pictures of MOS transistors (Scroll down to about the middle of the page)
• Lego Logic
• Off-topic but an example of a thorough report: An engineer's guide to cats

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