Publications

• Understanding bug fix patterns in verilog, Sangeetha Sudakrishnan, Janaki T. Madhavan, E. James Whitehead Jr., Jose Renau, Fith International Workshop on Mining Software Repositories, May 2008.
• Implementation of a Power Efficient High Performance FPU for SCOORE, Wael Ali Ashmawi, John Burr, Abhishek Sharma, Jose Renau, Workshop on Architectural Research Prototyping (WARP), held inconjunction with ISCA-35, June 2008.
• Measuring Power and Temperature from Real Processors, Francisco-Javier Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau, The Next Generation Software (NGS) Workshop (NGS08) held in conjunction with IPDPS, April 2008.
• uDSim, a Microprocessor Design Time Simulation Infrastructure. Sangeetha Sudhakrishnan, Francisco-Javier Mesa-Martinez, Jose Renau, Wild and Crazy Ideas VI (WACI) held in conjunction with ASPLOS, March 2008.
• Processor Verification with hwBugHunt, Sangeetha Sudhakrishnan, Liying Su, and Jose Renau, IEEE International Symposium on Quality Electronic Design (ISQED), March 2008.
• System and Processor Design Effort Estimation, Cyrus Bazeghi, Francisco J. Mesa-Martinez, and Jose Renau, Springer Research Trends in VLSI and Systems on Chip.

• Effective Optimistic-Checker Tandem Core Design Through Architectural Pruning, Francisco J. Mesa-Martinez and Jose Renau, 40th International Symposium on Microarchitecture (MICRO), December 2007.
• Estimating Design Time for System Circuits, Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, and Jose Renau, 15th IFIP International Conference on Very Large Scale Integration (VLSI-SoC), October 2007.
• Power Model Validation Through Thermal Measurements, Francisco J. Mesa-Martinez, Joseph Nayfach-Battilan, and Jose Renau, International Symposium on Computer Architecture (ISCA), June 2007.
• Measuring Performance, Power, and Temperature from Real Processors, Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, and Jose Renau, 1st Workshop on Experimental Computer Science (FCRC), June 2007.

• SEED Scalable, Efficient Enforcement of Dependences, Francisco J. Mesa-Martinez, Michael C.Huang, and Jose Renau, 15th International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2006.
• Printed Circuit Board Layout Time Estimation, Cyrus Bazeghi and Jose Renau, 7th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-33, June 2006.
• SCOORE Santa Cruz Out-of-Order RISC Engine, FPGA Design Issues, Francisco J. Mesa-Martinez, Abhishek Sharma, Andrew W. Hill, Carlos A. Cabrera, Cyrus Bazeghi, Hari Kolakaleti, Joseph Nayfach, Keertika Singh, Kevin S. Halle, Matthew D. Fischler, Melisa Nuñez, Sangeetha Nair, Suraj Narender Kurapati, Wael Ali Ashmawi, and Jose Renau , Workshop on Architectural Research Prototyping (WARP), held inconjunction with ISCA-33, June 2006.
• Using Checkpoint-Assisted Value Prediction to Hide L2 Misses, Luis Ceze, Karin Strauss, James Tuck, Jose Renau, and Josep Torrellas, ACM's Transactions on Architecture and Code Optimization (TACO), March 2006.
• POSH A TLS Compiler that Exploits Program Structure, Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau and Josep Torrellas, ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), March 2006.
• Energy-Efficient Thread-Level Speculation on a CMP, Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas, IEEE Micro Special Issue Micro's Top Picks from Computer Architecture Conferences, January-February 2006.

• uComplexity Estimating Processor Design Effort, Cyrus Bazeghi, Francisco J. Mesa-Martinez, and Jose Renau. 38th International Symposium on Microarchitecture (MICRO), November 2005.
• POSH A Profiler-Enhanced TLS Compiler that Leverages Program Structure, Wei Liu, James Tuck, Luis Ceze, Karin Strauss, Jose Renau, and Josep Torrellas. The Second Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=AC2), September 2005.
• Thread-Level Speculation on a CMP Can Be Energy Efficient, Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas. International Conference on Supercomputing (ICS), June 2005.
• Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors Microarchitecture and Compilation, Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, and Josep Torrellas. International Conference on Supercomputing (ICS), June 2005.

• CAVA Hiding L2 Misses with Checkpoint-Assisted Value Prediction, Luis Ceze, Karin Strauss, James Tuck, Jose Renau, and Josep Torrellas, IEEE TCCA Computer Architecture Letters (TCCA), Dec 2004.

• Managing Multiple Low-Power Adaptation Techniques The Positional Approach, Michael Huang, Jose Renau and Josep Torrellas, Sidebar on Special Issue on Power-Aware Computing, (IEEE Computer), December 2003.
• Positional Adaptation of Processors Application to Energy Reduction, Michael Huang, Jose Renau, and Josep Torrellas, International Symposium on Computer Architecture (ISCA), June 2003.
• Programming a Parallel Intelligent Memory System, Basilio B. Fraguela, Jose Renau, Paul Feautrier, David Padua, and Josep Torrellas, Symposium on Principles and Practice of Parallel Programming (PPoPP), June 2003.

• Cherry Checkpointed Early Resource Recycling in Out-of-order Microprocessors, Jose F. Martinez (Cornell University), Jose Renau (University of Illinois), Michael Huang (University of Rochester), Milos Prvulovic, and Josep Torrellas (University of Illinois), 35th International Symposium on Microarchitecture (MICRO), November 2002.
• Energy-Efficient Hybrid Wakeup Logic, Michael Huang, Jose Renau, and Josep Torrellas, International Symposium on Low Power Electronics and Design (ISLPED), August 2002.
• A Framework for Dynamic Energy Efficiency and Temperature Management, Michael Huang, Jose Renau, and Josep Torrellas Journal on Instruction Level Parallelism (JILP), 2002.

• Profiled-Based Energy Reduction for High-Performance Processors, Wei Huang, Jose Renau, and Josep Torrellas, 4th ACM Workshop on Feedback-Directed and Dynamic Optimization, December 2001.
• Energy/Performance Design of Memory Hierarchies for Processor-In-Memory Chips, Wei Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, 2nd Workshop on Intelligent Memory Systems, November 2000, Lecture Notes in Computer Science(Vol. 2107) by Springer-Verlag, 2001.
• Cache Decomposition for Energy-Efficient Processors, Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas , International Symposium on Low Power Electronics and Design (ISLPED), August 2001.

• A Framework for Dynamic Energy Efficiency and Temperature Management, Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, 33rd International Symposium on Microarchitecture (MICRO), December 2000.
• Memory Hierarchies in Intelligent Memories Energy/Performance Design, Wei Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, Ninth Workshop on Scalable Shared Memory Multiprocessors, June, 2000.