Evaluation of the Tensor Processing Unit: A Deep Neural Network Accelerator for the Datacenter

Speaker Name: 
David Patterson
Speaker Title: 
EECS Professor Emeritus and Professor in the Graduate School
Speaker Organization: 
UC Berkeley
Start Time: 
Friday, February 8, 2019 - 2:40pm
End Time: 
Friday, February 8, 2019 - 3:45pm
Scott Beamer


With the ending of Moore's Law, many computer architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. The Tensor Processing Unit (TPU), deployed in Google datacenters since 2015, is a custom chip that accelerates deep neural networks (DNNs).  We compare the TPU to contemporary server-class CPUs and GPUs deployed in the same datacenters. Our benchmark workload, written using the high-level TensorFlow framework, uses production DNN applications that represent 95% of our datacenters’ DNN demand. The TPU is  an order of magnitude faster than contemporary CPUs and GPUs and its relative performance per Watt is even larger.


David Patterson is a Berkeley CS professor emeritus, a Google distinguished engineer, and the RISC-V Foundation Vice-Chair. He received his BA, MS, and PhD degrees from UCLA. His Reduced Instruction Set Computer (RISC), Redundant Array of Inexpensive Disks (RAID), and Network of Workstation projects helped lead to multibillion-dollar industries. This work led to 40 awards for research, teaching, and service plus many papers and seven books. The best known book is Computer Architecture: A Quantitative Approach and the newest is The RISC-V Reader: An Open Architecture Atlas. In 2018 he and John Hennessy shared the ACM A.M Turing Award.