Assessing Reliability in Semiconductor Devices and Integrated Circuits

Speaker Name: 
Tanya Nigam
Speaker Title: 
Engineer, Global Foundries
Speaker Organization: 
Global Foundries
Start Time: 
Monday, May 6, 2019 - 10:40am
End Time: 
Monday, May 6, 2019 - 11:45pm
Engineering 2 - 192
Prof. Yu Zhang & Prof. Michael Wehner


Manufacturable process requires 3 critical elements: Performance, Yield and Reliability. In advanced technologies all of these are very closely linked and require careful optimization. Reliability assessment in advance nodes requires a detail understanding of materials, statistics, semiconductor device physics, nature and location of defects. As we continue to scale physical dimension, the electrical metrics do not scale proportionately requiring constant innovation in material to meet performance and reliability. As dimensions are reducing, variability is becoming a bigger concern requiring significant statistical analysis and modeling. Understanding the reliability degradation models requires close interaction with device/process optimizing and involves understanding key principles of semiconductor device physics. Novel device architecture are requiring additional characterization and modeling which need to comprehend product application space. End goal of reliability modeling on semiconductor devices is the ability to predict the useful life at product level. Scaling models and understanding from device level to product space and ability to predict is essential for future reliability engineers. All of these aspects will be discussed in the context of traditional scaling of CMOS roadmap and More than Moore.


Tanya obtained her PhD from IMEC in 1999 in EE in the area of semiconductor reliability and joined Bell Labs, Lucent Technology as a Post Doc in 1999. She became a Member of Technical staff in 2000 at Bell Labs and then joined the spin off Agere Systems. Since moving to Bay Area she has worked at Cypress Semiconductor, AMD and now at GLOBALFOUNDRIES in area of technology definition, reliability and transistor optimization.