Advancement: Designing Efficient Hardware Transactional Memory for Persistent Memory Systems

Speaker Name: 
Yuanjiang Ni
Speaker Title: 
PhD Student (Advisor: Ethan Miller)
Speaker Organization: 
Computer Science
Start Time: 
Friday, December 14, 2018 - 10:00am
End Time: 
Friday, December 14, 2018 - 12:00pm
Engineering 2, Room 380
Ethan Miller

Abstract:  Non-Volatile Random Access Memory (NVRAM) technologies are closing the performance gap between traditional storage and memory. Hardware Transactional Memory (HTM) simplifies the implementation of efficient concurrent programs. The combined power of HTM and persistent memory has the potential to enable drastic accelerations of modern storage systems. Since systems failures are inevitable, this model requires failure-atomicity mechanisms to ensure that persisted data is consistent, and hence really reusable. Straightforward combinations of the HTM and traditional failure-atomicity mechanisms cannot realize the full value of these new memory technologies. Our dissertation seeks to answer: i) how should the failure-atomicity mechanisms be re-designed in the context of persistent memory, ii) how to efficiently integrate the HTM with persistent memory. iii) how to facilitate the acceptance of our proposed techniques.

We intend to implement a PM-aware HTM in a full-system simulator that will allow us to explore these research questions. Our preliminary results show that the proposed failure-atomicity mechanism, called Shadow Sub-Paging, reduces the NVRAM writes by up to 2.7x and thus improves the performance by up to 1.9x.