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Determining the Optimal Size of a Reuse Buffer
Reducing Compilation Time of Zhong's FPGA-based SAT Solver
An Analysis of Potential CRC Polynomials Using Simulated
Bit Errors in Transmitted Packets
Determining Optimal Compression Effort For JPEG-LS Images
StockMaster: A Java-Based Stock Portfolio Manager
Complexity Analysis of a Massively Parallel Boolean Satisfiability
Implication Circuit
A Scalable, Loadable Custom Programmable Logic Device for
Solving Boolean Satisfiability Problems
Test CNF formulas for ELVIS sat solver
A Reading Test Demonstrating Sorting Properties of Parallelism
Related Publications:
Accelerating Boolean Satisfiability with Configurable Hardware
Related Conferences:
IEEE Symposium on Field-Programmable Custom Computing Machines
ACM International Symposium on Field-Programmable Gate Arrays
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