Chip Design & Packaging
In the sub-micron world of the computer chip, leading-edge challenges facing the industry are driving the next generation of research and innovation at the UC Santa Cruz School of Engineering. As chips themselves become smaller and smaller, they are growing in complexity. Moreover, the packages into which they are assembled are growing in density, and they are running at increasingly higher speeds. The challenges associated with these trends are the focus of a number of projects now underway at UC Santa Cruz in:
Wayne Dai
Professor of Computer Engineering
- Highly dense packaging,
- High-speed interconnects,
- Technology mapping, and
- Testing of highly complex systems.
Current research activities include the design, simulation and analysis of systems involving multiple technologies, such as the development of a field programmable multi-chip module that uses multi-chip technology to bring an order of magnitude increase in the density of field programmable logic devices. Researchers are also investigating issues associated with system interconnects at very high speeds, including optical interconnects and ways of dissipating the heat generated by these high-speed interconnections. In addition, work is underway to develop an architecture in which functional designs can be mapped into new technologies for future applications.
The Kestrel Research Project built a custom VLSI parallel processor that accelerates computational biology, computational chemistry, and other algorithms by factors of 20 to 40. The 512-processor single-board system is exceedingly effective at solving certain types of problems, such as gene sequence alignment and hidden Markov model training. A Smith-Waterman search engine is available online.
The speed and complexity of today's chips present unique testing challenges as well, challenges that UC Santa Cruz is leading the way in answering. In this area, we are developing advanced novel approaches to understanding the defect mechanisms of circuits in order to create unique and effective testing methods.
People
An array of experts has come together at the UC Santa Cruz School of Engineering to address the challenges at the cutting edge of today's industry trends. These specialists include:
Wayne Dai, whose research interests lie in computer-aided design of VLSI chips, including layout synthesis and interconnect analysis, and multi-chip modules.
Pak Chan and Martine Schlag, who specialize in partitioning, placement and routing of field-programmable gate array-based systems.
Joel Ferguson and Tracy Larrabee, who lead the SCTest Group.
Richard Hughey, working on the Kestrel parallel processor.
Ali Shakouri, a specialist in quantum electronics, who has focused on integrated cooling of electronic components.
Research
Kestrel, a custom VLSI parallel processor with 512 processing elements on a single board.
Quantum Electronics, focused on efficient heat removal or thermal design of electronic, optoelectronic, and micro-electro- mechanical (MEMS) devices.
SCTest, research in testing, testability, and diagnosis of integrated circuits.