CE110:  Computer Architecture

Introduction to computer architecture, including examples of 
current approaches and the effect of technology and software.  
Computer performance evaluation, basic combinatorial and 
sequential digital components, instruction set architectures, 
MIPS ISA and RISC paradigm, single-cycle, multicycle and 
pipelined CPU architectures, cache and virtual memory. May 
include advanced topics such as parallel processing, MIMD, 
SIMD, VLIW.  
Prerequisites: CMPE12.

Explanation of prerequisites
CMPE12:  Introduction to computer organization and assembly.

Required skills to pass the course
1)  Choose the appropriate method to measure computer performance
    and to compare performance of different computers or applications.
2)  Understand both integer and floating-point computer arithmetic.
3)  Use digital devices to build basic computing machines, and use 
    basic blocks to build complex computing machines, increasing the 
    word size and/or the performance.
4)  Recognize different Instruction Set Architectures (ISA) and 
    their advantages and disadvantages with respect to coding 
    efficiency and implementation efficiency.
5)  Implement a basic RISC ISA (MIPS) as single-cycle, multicycle, 
    and pipelined, understanding the tradeoffs of these approaches 
    and in particular the issues and techniques related to pipelining 
    (hazards, forwarding, and branch prediction).
6)  Analyze and understand a memory system with a cache, with and 
    without virtual memory.
7)  Apply basic coding techniques to improve program performance 
    in systems with a cache and/or virtual memory.

Core topics (must be taught)
1)  Performance measures: clock frequency, CPI, IPC, MIPS, MOPS, 
    FLOPS. Combining of benchmarks: total run time, arithmetic mean, 
    weighted arithmetic mean, geometric mean. SPEC benchmarks. 
    Amdahl's law.
2)  Basics of digital design: logic functions and logic gates,
    multiplexers, CMOS gates, propagation delay time,
    flip-flops, decoders, registers, timing diagrams. Bitwise logical 
    operation.
3)  Number representations: integer and floating-point.
4)  Design of adders: ripple-carry, carry-lookahead, carry-select.
5)  Design of multipliers: shift-and-add, array. Booth's algorithm 
    in Radix-2 and  Radix-4. 
6)  Binary division and design of integer dividers: restoring and 
    non-restoring.
7)  Instruction set design and analysis: stack, accumulator, and
    general-purpose register architectures.
8)  RISC concepts and MIPS instruction set architecture
9)  Instruction set implementation. Design of an ALU and use of 
    multiplexors to create reconfigurable datapaths.
10) MIPS single-cycle implementation and analysis.
11) MIPS multicycle implementation and analysis.
12) MIPS pipelined implementation and analysis.
13) Pipeline hazards: types, effect on performance.
14) Pipeline forwarding.
15) Branch and jump processing, static and dynamic branch 
    prediction and speculative execution. Delayed branches.
16) Basic compiler optimization techniques.
17) Memory hierarchy. Cache, different cache organizations: 
    direct-mapped, set-associative, fully-associative. 
    Effect of cache on performance.
18) Virtual memory and TLB, and its integration with a cache.
19) Analysis of Average Memory Access Time (AMAT).	  
20) Cache-friendly programs.	

Optional topics
1)  Additional computer arithmetic: floating-point division 
    (SRT, Newton-Raphson, Goldschmit), high-radix Booth's algorithm 
    and Booth-encoded floating-point hardware multiplier.
2)  Manchester carry chain adder, carry-save adder, stuck-at 
    fault modeling.
3)  Floating-point rounding methods and implementation (guard, 
    round and sticky bits).
4)  Advanced CPU architectures and techniques: super-pipelined, 
    super-scalar, out-of-order execution, multi-threaded, VLIW.
5)  Advanced memory techniques to reduce the AMAT.
6)  Parallel computer architectures: MIMD, SIMD, clusters, etc.

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Original by Richard Hughey, August 2001
Updated by Andrea Di Blas, October 2004