UCSC Course CE125 Logic Design with Verilog Each of our courses has an extended description, a list of the ABET outcomes that course helps fulfill, and some sample coursework.

CE 125 has an extended course description, it fulfills these ABET outcomes (as determined by Pak Chan, Cyrus Bazeghi, and Richard Hughey),

• Outcome a via Skill 1, 2, Core Topics 1 through 9, and Core Lab Exercises 1 thorugh 3
• Outcome b via Skill 1, Core Topic 7, and Core Lab Exercises 1 through 3
• Outcome c via Skill 1, Core Topics 1, 5, 7, and Core Lab Exercises 1 thorugh 3
• Outcome e via Skill 1, Core Topics 1, 3, 4, 5, 7, and Core Lab Exercises 1 thorugh 3
• Outcome k via Skills 1, 2, Core Topics 2, 6, 7, 8, 9, and Core Lab Exercises 1 thorugh 3
• Professional Component b via all skills, topics, and exercises
• Major Design Experience via all skills, topics, and exercises

• The final project report from a student at the top of the class
• The final project report from a student at the middle of the class