Associate Professor, Computer Engineering

Baskin School of Engineering
1156 High St
Mail Stop SOE2
Santa Cruz, CA 95064

Phone Number: 831-459-4449 (Office)
Phone Number: 831-406-1851 (VoIP)

Department: Computer Engineering

Office Location: Engineering 2, Room 225
Office Hours: By email/appointment

E-Mail Address:

Web Pages

• Matthew Guthaus' Personal Page
• VLSI Design Automation Group

Degrees

• Ph.D. in Electrical Engineering, 2006, The University of Michigan
• MSE in Electrical Engineering, 2000, The University of Michigan
• BSE in Computer Engineering, 1998, The University of Michigan

Biography

Matthew Guthaus received his BSE in Computer Engineering in 1998, MSE in 2000, and PhD in 2006 in Electrical Engineering from The University of Michigan (UM). Matthew is currently an Assistant Professor at the University of California Santa Cruz in the Computer Engineering department. Matthew is a member of ACM, IFIP Working Group 10.5, and a Senior Member of IEEE. His research interests are in high-performance and low-power clock distribution; design for variability and reliability; and computer-aided design of Integrated Circuits. Matthew is the recipient of a 2011 NSF CAREER award and a 2010 ACM SIGDA Distinguished Service Award. He is also the Director of the UCSC Summer Undergraduate Research Fellowship in IT (SURF-IT), a NSF-sponsored Research Experience for Undergraduates (REU) site.

Research Areas

VLSI, CAD, design for reliability and variability, resonant clocking, sub-threshold circuits

Selected Publications

• W. Condley, X. Hu, M.R. Guthaus. A Methodology for Local Resonant Clock Synthesis using LC-Assisted Local Clock Buffers, International Conference on Computer-Aided Design (ICCAD), San Jose, CA, 2011, to appear.
• X. Hu, M. R. Guthaus, Distributed Resonant Clock Grid Synthesis (ROCKS), Design Automation Conference (DAC) , San Diego, CA, 2011.
• S. Kim, M.R. Guthaus. Low-Power Multiple-Bit Upset Tolerant Memory Optimization, International Conference on Computer-Aided Design (ICCAD), San Jose, CA, 2011, to appear.
• M. R. Guthaus, G.R. Wilke, R. Reis, Non-Uniform Clock Mesh Optimization with Linear Programming Buffer Insertion, Design Automation Conference (DAC), 2010.
• S. Kim, M. R. Guthaus, Leakage-Aware Redundancy for Reliable Sub-threshold Memories, Design Automation Conference (DAC) , San Diego, CA, 2011.

Current and Future Classes

Spring 2012

• CMPE 100: Logic Design
• CMPE 100L: Logic Design Laboratory
• CMPE 280G: VLSI/CAD Seminar

Fall 2012

• CMPE 12: Computer Systems and Assembly Language
• CMPE 12L: Computer Systems and Assembly Language Laboratory
• CMPE 280G: VLSI/CAD Seminar

Winter 2013

• CMPE 125: Logic Design with Verilog
• CMPE 125L: Logic Design with Verilog Laboratory
• CMPE 280G: VLSI/CAD Seminar

Spring 2013

• CMPE 222: VLSI Digital System Design
• CMPE 280G: VLSI/CAD Seminar

Students & Researchers

• Brian Chen (Undergraduate)
• Ryan Conway (Undergraduate)
• Seokjoong Kim (Graduate)
• Benjamin LaCara (Undergraduate)
• Ian Lee (Graduate)
• Sheldon Logan (Graduate)
• Rajsaktish Sankaranarayanan (Graduate)
• Marcelo Siero (Graduate)

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