CMPE 225, P.K. Chan University of California, Santa Cruz, Fall 98

Introduction to ASIC Systems Design
Course Outline

Objectives :

To learn elementary application specific design techniques, use of CAD design tools, and to study the state-of-the-art in applications of application specific machines (custom computing machines).

When and Where:

TTh 2:00-3:45 Applied Sciences 372

Required readings:

CMPE 225 reader, I will put one copy in the technical library in Applied Sciences. This is NOT available from the campus copying center. Since this is a graduate-standing class, you will critique research papers.

Prerequisite:

CE100 logic design; CE202 computer architecture is strongly recommended. Reasonable backgrounds in combinational and sequential logic design (Karnaugh maps, state diagrams and reduction etc), basic engineering circuit knowledge (like Ohm's Law V=IR, power consumption, current sink and source), and ability to read a simple data sheet are assumed. Basic laboratory skill (multimeter, oscilloscope, ..), C programming, and DOS shells.

Instructor:

Pak K. Chan, Applied Sciences 325, phone: 459-4156, <pak@cse.ucsc.edu>

Office Hours: Friday 2:00-3:00, or by appointment.

Grading: You must turn in ALL homeworks.

• 35% 3 Homeworks, (late homeworks will not be accepted) including two paper critiques.
• 40% Design project complete on Dec 11, 1998 and report due 5:00pm Dec 16, 1998.
• 25% late mid-term (a mini project) (6th week).
• Participate in discussion in class, and give one presentation in class by the end of the quarter.

Incomplete will only be given for reasons of illness, jury duty, family problems, and natural disasters. A supporting document from your physician/family member is necessary.

Policy concerning final project

There are no excuses for late, nonfunctional, or incomplete projects. Incomplete projects will lead to No Pass grades.

Policy concerning homeworks:

I'll hand out the homeworks in lecture and each homework assignment must be due 14 days later. Your homework will be graded (though not necessarily corrected).

Design Project:

A complete system (hardware + software) design and verification of a ``digital system'' (TBA) project. In the past, I had assigned ``mine sweeper'', and ``maze runner'' projects.

Lab Facilities:

Applied Sciences 240. Please keep it clean (i.e., no food and drinks) ALL the time. PC computers are loaded with Xilinx tools, PC (turboC) compilers, some PCs will be used for prototyping, Borg II prototyping boards are also available. Four Tektronix digital oscilloscopes.

Computer Account:

grad accounts on any cse machines.

Key dates

        Topics                                                Readings

Oct      1      introduction
         6      Overview gate array vs standard cell
                technology
         8      XC3000 and XC4000 FPGAs                       data book
        13      FPGA design flow and tools                    text, chp 3
        15      FPGA design guidelines                        class notes
                define final project

        20,22   Bdsyn description language                    reader
        27,29   mis/sis logic minimization tool               text chp 5

Nov     3       mis/sis logic minimization tool               reader
        5       state machine and state assignment            text chp 6
        10      midterm due
        12      midterm report due
        17      placement and routing      
        19      partitioning, routability, wire length models  reader
        20      final project definition and review
        24      FPGA-based custom machines                     reader
        26      Thanksgiving, no class

Dec     1,3     FPGA-based custom machines                     reader
        8,10    class presentations

        11      Project Demo
        16      Submit written project report

Tentative Course Outline

• Implementation media: System design overview, management of large scale design, random logic based, gate-array based design -- Xilinx tools: Viewdraw, Viewsim, XACT, APR, PPR. Architectures of Xilinx programmable gate arrays FPGA. Architectures of Actel programmable gate arrays FPGA.

• Design specifications: A logic description language: Bdsyn.

• Design flow: Entry tools, technology mapping, placement and routing, programming.

• Guidelines to ASIC designs: design guidelines/considerations

• (Basic) Combinational logic design: Boolean minimization tools -- espresso, misII, and SIS.

• (Basic) Finite state machines (FSM) design: state encoding, cooperative FSMs, FSM state minimization tools tools -- stamina, and mustang

• FPGA-based custom machines systems: PAM, Ganglion, SPLASH, BORG, Anyboard, Quickturn, Champ, Virtual wire.

• Timing issues and clocked system design: metastability, synchronization problem, clock skew, hazards, clock rate, retiming, systolic arrays.

• System design tools -- Partitioning and routability issues: Partitioning methods, wire length estimation, routability models, technology mappings, placement and routing tools.