CMPE 225, P.K. Chan University of California, Santa Cruz, Fall 2001

Introduction to ASIC Systems Design
Course Outline

Objectives :

To learn elementary application specific design techniques, use of CAD design tools, and to study the state-of-the-art in applications of application specific machines (custom computing machines). Introduction to system prototyping using Field-Programmable Gate Arrays (FPGAs). Topics include architectures of FPGAs, behavioral design specification, system partitioning, synthesis tools, design verification, and studies of novel systems implemented with FPGAs. Intended to familiarize students with the techniques and tools in ASIC designs. Final project is the complete design of a small system using FPGAs.

How to :

• Read this before you do homework 1

  Enter a simple design using a drawing tool

• A simple case of hierarchical design

• Translate a pla file into an XNF file

• Create a MACRO block in schematic/drawing that use an XNF file

• Create a MACRO block in schematic/drawing that use a Verilog file

• Create a Finite-State Machine MACRO block in schematic/drawing that use a Verilog file

• Create a bit stream for an FPGA that does nothing

• Create a MCS file to download to BORG board

• Build a C program to talk to a BORG board

• How to create a hardmacro ?

• Software SAT solver SATO.uu

BORG Crib Sheet : Crib

Verilog References:

• Synplicity User's Guide (pdf)

• Synopsys/FPGA Express Reference manaul (pdf)

• Xilinx Floor-planner Reference manaul (pdf)

• Silly Synplificty FSM examples

• On-Line Verilog manual: link

Homeworks:

Homework 1 Due Oct 4

Homework 1.5 Due Oct 18

Midterm Due Oct 30

When and Where:

TTh 12:00-1:45pm Crown College 104, will move to Baskin Engineering 111 later

Required readings:

There is NO text book. There is a reader. I will give one copy to your class representative on the second day of class. The reader contains some data sheet, research papers, crib sheet etc. Talk your class representative regarding distribution of the reader. This is NOT available from the campus copying center. Since this is a graduate-standing class, you will critique two research papers.

Prerequisite:

CE100 logic design; CE202 computer architecture is strongly recommended. Reasonable backgrounds in combinational and sequential logic design (Karnaugh maps, state diagrams and reduction etc), basic engineering circuit knowledge (like Ohm's Law V=IR, voltage, current, power consumption, current sink and source), operational amplifier, and ability to read a simple data sheet are assumed. Basic laboratory skill (multimeter, oscilloscope, signal generator), C programming, and DOS/command shells.

Instructor:

Pak K. Chan, Baskin Engineering 325, phone: 459-4156, <pak@soe.ucsc.edu>

Office Hours: Wednesday 1:00-2:00, or by appointment.

TA, Custodian, Janitor: same as above.

Grading: You must turn in ALL homeworks.

• 30% 2.5 Homeworks, (late homeworks will not be accepted) including two paper critiques.
• 40% Design project complete on 5:00pm Dec 4, 2001 and report due 5:00pm Dec 6, 2001.
• 25% late mid-term (a mini project) (6th week).
• 5% Participate in discussion in class (paper critique), and give one presentation in class by the end of the quarter.

Incomplete will only be given for reasons of illness, jury duty, family problems (a supporting document from your physician/family member is necessary for this reason), and natural disasters.

Policy concerning final project

There are no excuses for late, nonfunctional, or incomplete projects. Incomplete projects will lead to No Pass grades.

Academic Integrity

Thou shall not cheat. Any (in form or in spirit) misrepresentation of your work is cheating.

Policy concerning homeworks:

I'll hand out the homeworks in lecture and each homework assignment must be due about 10 days later. Your homework will be graded (though not necessarily corrected).

Design Project:

A complete system (hardware + software) design and verification of a ``digital system'' (TBA) project. In the past, I had assigned ``mine sweeper'', ``maze runner'', SAT engines projects.

Lab Facilities:

Baskin Engineering Lab 111. Please keep it clean (i.e., no food and drinks) ALL the time. Failure to observe this policy will automatically lead to NO Pass grade. PC computers are loaded with Xilinx tools, MicroSoft compiler, Borg II prototyping boards are also available. Your primary debugging tool will be Tektronix digital oscilloscopes.

Computer Account:

grad accounts on any soe solaris machines.

common accounts on any lab NT machines. Please keep your work on a private removable floppy/zip disk.

Key dates

        Topics                                                Readings

Sep     20      Introduction
        25      Overview gate array vs standard cell
                technology
        27      XC4000 FPGAs                                   data book

Oct     2       FPGA design flow and tools                     Ref1, chp 3
        4       FPGA design guidelines                         class notes
                define final project

        9,11    HDL description language                       reader
        16,18   mis/sis logic minimization tool                Ref1 chp 5

        23      mis/sis logic minimization tool                reader
        25      state machine and state assignment             Ref1 chp 6
        30      midterm due
 
Nov     1       midterm report due
        6       placement and routing      
        8       partitioning, routability, wire length models  reader
        13      final project definition and review
        15,20   FPGA-based custom machines                     reader
        22      Thanksgiving, no class
        27,29   class presentations (paper critique talks)

Dec     4      Project Demo (5pm)
        6      Submit written project report (5pm)

Ref1: Digital Design Using Field-Programmable Gate Arrays, Chan/Mourad ,Prentice Hall, 1994.

Tentative Course Outline

• Implementation media: System design overview, management of large scale design, random logic based, gate-array based design -- Xilinx tools: Foundation, Schematic, simulation, FPGA editor. Architectures of Xilinx programmable gate arrays FPGA. Architectures of Actel programmable gate arrays FPGA.

• Design specifications: A Hardware description language: Verilog.

• Design flow: Entry tools, technology mapping, placement and routing, programming.

• Guidelines to ASIC/FPGA designs: design guidelines/considerations

• (Basic) Combinational logic design: Boolean minimization tools -- espresso, misII, and SIS.

• (Basic) Finite state machines (FSM) design: state encoding, cooperative FSMs, FSM state minimization tools tools -- stamina, and mustang

• FPGA-based custom machines systems: PAM, Ganglion, SPLASH, BORG, Anyboard, Quickturn, Champ, Virtual wire, SAT engines.

• Timing issues and clocked system design: metastability, synchronization problem, clock skew, hazards, clock rate, retiming, systolic arrays.

• System design tools -- Partitioning and routability issues: Partitioning methods, wire length estimation, routability models, technology mappings, placement and routing tools.