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Lecture Make-Up

I will be missing two classes on 1/22 and 1/24 to present at ASP-DAC in S. Korea. Instead of trying to find a common time to make-up these lectures, I am requiring that everyone attend 2 sessions of 280G and turn in two 1 page summaries/critiques of two papers by the last day of class (March 13, 5pm). These summaries/critiques should briefly summarize the problem addressed and how it is solved. More importantly, it should perform a critical analysis of the solution, evaluation, and results.

Lectures

# MM/DD Topic Slides Reading/Assignment
1 01/08 Introduction to HDLs 01intro
2 01/10 Verilog 02verilog
3 01/15 Verilog (continued)/Synthesis 03synthesis
4 01/17 Synthesis (continued) DC Tutorial, Paper 5, Paper 6
5 01/22 NO CLASS -- must summarize 1 280G paper to make-up by end of quarter 280G paper
6 01/24 NO CLASS -- must summarize 1 280G paper to make-up by end of quarter 280G paper
7 01/29 Static Timing Analysis 04sta Paper 1
8 01/31 SSTA, Start PLI 05pli
9 02/05 Finish PLI, SystemVerilog 06systemverilog
02/07 Quiz 1 - "Front End" Design
10 02/12 Review Quiz, Finish SystemVerilog
11 02/14 Synchronization (metastability, synchronizer design) 07synchronization Dally 10.1-10.3
12 02/19 Advanced Clocking (clock distribution, PLLs, two-phase, useful skew, clock gating) 08clocking Dally 9.5-9.7, Paper 2
13 02/21 Finish Advanced Clocking
14 02/26 Power Distribution (IR drop, bypass caps,etc.) 09power Dally 5.1-5.5
15 02/28 Power Analaysis & Optimization (switching analysis) 10poweropt Paper 3
16 03/04 Signaling (current-mode, differential, low-swing, wishbone) 11signal Dally 7.1-7.5
17 03/06 Advanced Sequential Circuits 12sequential Paper 4
03/11 Quiz 2 - "Back End" Design
18 03/13 Guest Lecture
19 ? Design for Test
18 ? Mixed Signal Modeling (Verilog-A)

Additional Papers

You must be on-campus to retrieve these papers or you must go through the library's proxy server from off-campus.
  1. C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, S. Narayan. First-order incremental block-based statistical timing analysis. In DAC, pages 331--336, June 2004.
  2. John P. Fishburn. Clock Skew Optimization. IEEE Trans. Computers 39(7): 945-951 (1990)
  3. A. Farrahi, C. Chen, A. Srivastava, G. Tellez, M. Sarrafzadeh. Activity-Driven Clock Design, IEEE Transactions on CAD/ICAS, Vol. 20, No. 6, pp. 705-714, June 2001.
  4. Vladimir Stojanovic and Vojin G. Oklobdzija. Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems, IEEE Journal of Solid-State Circuits, Vol. 34, No. 4, April 1999, pp. 536-548.
  5. Not required, but for clarification: C. Cummings, "full_case parallel_case", the Evil Twins of Verilog Synthesis, SNUG 1999.
  6. Not required, but for clarification: C. Cummings, Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!, SNUG 2000.