CMPE126: Advanced Logic Design / Winter 99

CMPE126 Home Page is under construction !

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Requesting academic accommodations:

If you would like to request academic accommodations due to a disability, please contact the Disabled Resource Center , 146 Hahn Student Services, (831)459-2089(voice) (831)459-4806(TDD/TTY). They can authorize specific accommodations for you in CMPE126 on an Accommodation Request Form. Please present this form to me early in the quarter so that we can discuss the accommodations you might need for class. You will need to see me again at least three weeks before each exam to arrange for testing accommodations.  

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Course Information

• Time and Place: MWF 9:30-10:40am Applied Sciences 169
• Lab hours: Applied Sciences 240: Tu ?-?pm
• Prerequisite: CMPE100, CMPE121
• Staff:
• Instructor: Pak K. Chan
  Location: Applied Sciences 325 Phone: (831)459-4156
  Office Hour: Tues. ??-??
• Lab Assistant: Nobody
• Grading: You must turn in ALL homeworks.

  • 30% 3 or 4 Homeworks, (late homeworks will not be accepted)
  • 30% late mid-term (a mini project) (6th week).
  • 40% Design project complete on March 12, 1999 and report due 5:00pm March 17, 1999.

    You will receive the same grade for both CMPE126 and CMPE126/L

  Incomplete will only be given for reasons of illness, jury duty, family problems, and natural disasters. A supporting document from your physician/family member is necessary.

  Policy concerning final project
  There are no excuses for late, nonfunctional, or incomplete projects. Incomplete projects will lead to No Pass grades.

  Policy concerning homeworks:
  I'll hand out the homeworks in lecture and each homework assignment must be due 14 days later. Your homework will be graded (though not necessarily corrected).

  Design Project:
  A complete system (hardware + software) design and verification of a ``digital system'' (TBA) project. In the past, I had assigned ``mine sweeper'', and ``maze runner'' projects. This is one of the capstone courses. You are doing your senior thesis in this class. This is a class to certify/qualify you to work professionally as an engineer. Most of the time, you should treat yourself, and I will treat you with the behavior and professionalism expected of entry-level engineers. Therefore, the passing criteria of the class are: design competence, promptness or punctuality, reliability, and honesty. Design competence means the ability to perform correct and well-principled digital design, debug digital designs, command of equipment (logic analyzer, oscillocope, multimeter, and signal generators), and to document designs. Any less than professional behavior will lead to immediate disqualification from this class.

• Text: Digital Design Using Field-Programmable Gate Arrays Prentice-Hall 1993.
  Reader: CMPE126 Reader, a collection of tutorials and data sheets
  Reference: Borg II User's Guide by Pak K. Chan with many helps from former UCSC students
  

• Topics

                                                                       
  
                                                                           When ?
     System design overview:
        management of large scale design, random logic based,
        gate-array based design -- Xilinx XC3000/XC4000 tools,             wk1-2
        Viewdraw, Viewsim, XACT, PPR, Xdelay, XNFBA, viewgen
  
     Field-Programmable Gate Arrays:                                       wk1-2
        Architectures of Actel and Xilinx programmable gate arrays
  
     Design Guidelines, design flow, debug
       design entry tools, technology mapping, placement and routing, 
       programming, oscilloscope
  
     Design specification:                                                  wk3
        A logic description language: Bdsyn
  
     Combinational logic design:
        Boolean minimization tools -- espresso, SIS
  
     Finite state machines (FSM) design:
        state assignment, state minimization, Mealy and Moore machines,
        state encoding programs, one-hot encoding, design of counters       midterm
  
     Timing issues and clocked system design:
        setup time and hold time, metastability, synchronization problems,
        clock skew and races, hazards, clock generation, clock rate
   
     Design Interface:
        PC interface, port I/O and interrupts, SRAM interface
  
     Design Prototyping: Borg boards
  
     System Design:
        partitioning a large design across chips, making all the parts
        work together
  
  

Homework Assignments

• Homework 1 : due ???, beginning of class.

Handouts

1. PORT304.zip (zip file)
2. Borg's Equation(postscript)

Academic Integrity: