CMPE126: Advanced Logic Design / Spring 2004

(Last Update: 05/26/04)

Final
Project demo due on 2:00pm June 4, 2004
Final report due 4:00pm June 10, 2004.

How to

• view the contents of a RAM during simulation

• use espresso and sis after the worm

• example using RAM symbols

• control and interact with the BORG from the PC

• interface the BORG board and the PC

• wire up the Borg board (Borg crib sheet)

• make a bitstream for an ``empty'' FPGA

• create an MCS file and download it to the BORG board

• convert a PLA file to an XNF file

• incorporate an XNF file as a MACRO in Foundation Schematic

• use the Project Manager (CMPE100 Lab 1)

• use the Xilinx 4000 Demonstration Board

Homework Assignments

• Homework 4: due Friday April 23 beginning of class.
• Homework 3: due Monday April 19 beginning of class.
• Homework 2: due Friday April 9 beginning of class.
• Homework 1 : due Monday April 5 beginning of class.

Slides on

• Flip Flops

• Fixing glitches

• Multi-level logic minimization

• Two level logic minimization

• Stop Watch Design Example

Course Information

• Requesting academic accommodations

• Time and Place: MWF 2:00-3:10pm BE150
• Lab: BE150
• Prerequisites: CMPE100, CMPE121, CMPE185 and passing CE Core exam
• Staff:
• Instructor: Martine Schlag
  e-mail: martine@cse.ucsc.edu
  Location: BE 317B Phone: (831)459-3243
  Office Hours: Wednesday 10-11am Friday 10-11am

• Lab Tutor: Angela Schmid
  e-mail: ang@cse.ucsc.edu


• Optional Text: Digital Design Using Field-Programmable Gate Arrays Prentice-Hall 1993.
  Reference: Borg II User's Guide (postcript)   (pdf) by Pak K. Chan with lots of help from former UCSC students
  
• Topics
• Grading and Coursework Policies Please read !!

Academic Integrity: