CMPE 125: Logic Design with Verilog
Fall 2007
Syllabus and General Information
Course Schedule
Lectures: TuTh 10:00 – 11:45, Earth & Marine Sciences B214
Lab: Baskin Engineering Room 115 (needs keycode for access)
Instructor
Anujan Varma, Professor, Computer Engineering
Office: E2-221, phone: (831) 459-3505
E-mail: varma@cse.ucsc.edu
Office Hours: Tue 1:00 – 2:00
Course Description
This course teaches the important concepts and methods in the design of digital systems using Hardware Description Languages (HDLs). We will primarily use Verilog as the HDL. The focus of the class will be on design techniques. Starting from the design of basic building blocks (combinational logic, state machines, etc.) we will go on to more complex designs (pipelined control units, synchronous and asynchronous FIFOs, etc.), ending with a major project.
In the accompanying lab, you will simulate your designs (using ModelSim), synthesize them for Altera FPGAs (using Quartus and Synplify Pro), and verify them on Altera FPGA boards.
Prerequisites
CMPE 121/L. You must enroll in both 125 and 125L in the same quarter.
Text
C. Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis,” Prentice-Hall, 2003.
Additional Reading
- M. D. Ciletti, “Advanced Digital Design with the Verilog HDL,” Prentice-Hall, 2002.
- Smith and Franzon, “Verilog styles for synthesis of digital systems”, Prentice-Hall, 2000.
In addition, several online resources are listed and linked on the course Website.
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Schedule of Topics
Week Date
Topic
Project
1 9/27
Introduction
2 10/2
Verilog syntax and examples
3 10/9
Design of basic building blocks
4 10/16
Design flows, verification methodology, FPGA design, tools
Project 1
5 10/23
State machines, data pipelines, etc.
Project 1
6 10/30
Advanced design techniques and examples
Project 2
7 11/6
Major project discussion
Project 2
8 11/13
Designs with multiple clock domains, async FIFO design
Major Project
9 11/20
Timing analysis
Major Project
10 11/27
SystemVerilog
Major Project
11 12/4
Major project discussion
Major Project
12 12/11
Finals Week
Project Demo on 12/11
Projects 1 and 2 will be done individually. The major project may be performed by teams of 2. Detailed reports are required for each of the projects.
Evaluation Criteria
Project 1: 20%
Project 2: 20%
Major Project : 60%
Honor Code:
Projects 1 and 2 must be done individually and all work submitted must be your own. Any collaboration in the major project must be limited to the other member of your team. Any incidents of academic dishonesty will be handled according to University policies and may cause you to fail the class.
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