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Jack Baskin School of EngineeringUC Santa Cruz

CMPE 125


Digital logic design, system-level design using current state of the
art in CAE tools. Students learn to design large-scale logic circuits
from fundamental building blocks and methods with the help of tools
used by professionals in the field today. All examples and assignments
will use the Verilog Hardware Description Language. Prerequisite(s):
courses 121 and 121L; concurrent enrollment in course 125L. Students
required to pass computer engineering core exam in first week of class
to remain enrolled. Enrollment limited to 20. P. Chan, A. Varma

(sourced from /cse/classes/cmpe125/description.txt)