CMPE100/L
Logic Design

Welcome to the evolving 100 Home Page

Grades have been posted in AIS (my.ucsc.edu) and scores are available in Canvas.
Have a good break!

Discussion: Piazza cmpe100/L forum ( to sign up for Piazza)

Homework Assignments

• Homework 6: due Friday March 15 in Canvas at 10pm PDT.
• Homework 5: due Wednesday February 27 in Canvas at 10pm PST.
• Homework 4: due Sunday February 17 in Canvas at 10pm PST.
• Homework 3: due Wednesday January 30 in Canvas at 10pm PST.
• Homework 2: due Friday January 25 in Canvas at 10pm PST
• Homework 1: due Wednesday January 16 in Canvas at 10pm PST.
(Solutions will be available in Canvas under Files)

Labs

• Lab 8
• Lab 7
• Lab 6
• Lab 5
• Lab 4
• Lab 3
• Lab 2
• Lab 1

Course Resources

• Slides
• Lab Write-Ups
• Your Engineering Notebook
• Lab resource page
(includes directions for installing lab software on your Windows or Linux PC)
(software now available on ITS PCs as well)
• Lab policies (a must read!)
• Topic, homework and reading schedule
• Text: Fundamentals of Digital Logic with Verilog Design by Stephen Brown and Zvonko Vranesic.
  First or Second or Third Edition
  McGraw-Hill 2013. ISBN-13: 978-0073380544 or ISBN-10: 0073380547 (these are the ISBNs for the third edition)
  

  There are several options for acquiring the text:
  But make sure the version you get says Verilog and not VHDL.

  1. Buy a new or used version of any edition from ??? for ???
  2. Not sure yet if the bookstore is carrying it this quarter.
  3. Rent the e-book version of the custom text through the bookstore.
  4. Buy the e-book version of this text from McGraw-Hill.

Course Information

• Lecture: MWF 9:20-10:25pm Thimann Lect 001
• Lab: Baskin Engineering 104.
  • Section 1A TuTh 9:50-11:40am
  • Section 1B TuTh 11:40-1:30pm
  • Section 1C TuTh 1:30-3:20pm
  • Section 1D TuTh 3:20-5:10pm
  You must attend at least the first meeting of your section each week and you will probably need to attend the second as well.
  You may work in the lab at other times (and you will need to!).
  Installing the Vivado Webpack on your windows or linux computer will make you less dependent on the lab. If you bring your laptop to the lab we can help you install it. If you have a Mac you can run Vivado by installing Windows using Bootcamp or a Virtual environment such as VMWare.
• LSS Small Group Sessions: Sign up at https://sserc.ucsc.edu/slug-success
  • Tuesday 5:30pm - 6:30pm in Jack's Lounge
  • Wednesday 12:00pm - 1:00pm in Jack's Lounge
  • Thursday 2:45pm - 3:45pm in Jack's Lounge

• Staff:
• Instructor: Martine Schlag
  e-mail: martine followed by @soe.ucsc.edu
  Office Hours: Wednesday 3:00-4:00pm and Thursday 3:00-4:00pm
  except on W 1/30 it is 12:30-1:30pm
  E2 219 (northwest corner), (831)459-3243
• TAs:
  • Krystine Carrington e-mail: kmcarrin followed by @ucsc.edu
  • Jason Ting e-mail: jting2 followed by @ucsc.edu
• Lab Tutors:
  • Michael Wai Chan e-mail: wakchan followed by @ucsc.edu
  • Hunter Coffman e-mail: hcoffman followed by @ucsc.edu
  • Andy Kang e-mail: mykang followed by @ucsc.edu
  • Sarah Mitchell e-mail: sacmitch followed by @ucsc.edu
  • Thomas Nijssen e-mail: tnijssen followed by @ucsc.edu

• SSI tutor:
  • Phu Le e-mail: phvle followed by @ucsc.edu

• Grading
• Pre-requisite: CMPE12/L
• Requesting academic accommodations

Other Information

• Academic Integrity
• SOE home page
• FPGA FAQ
• Murphy's Law
• Unacceptable proof techniques
• Direction of current flow (the holes have it!)
• Pictures of MOS transistors (Scroll down to about the middle of the page)
• Lego Logic
• Off-topic but an example of a thorough report: An engineer's guide to cats

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