CMPE100/L
Logic Design

Welcome to the evolving 100 Home Page

Winter 18 CMPE 100/L is over.

Grades have been posted in AIS and scores are available in Canvas.
Have a good break!

Discussion: Piazza cmpe100/L forum ( to sign up for Piazza)

Homework Assignments

• Homework 6: due Friday March 16 in Canvas at 10pm PDT.
• Homework 5: due Wednesday February 28 in Canvas at 10pm PST.
• Homework 4: due Sunday February 18 in Canvas at 10pm PST.
• Homework 3: due Wednesday January 31 in Canvas at 10pm PST.
• Homework 2: due Friday January 26 in Canvas at 10pm PST
• Homework 1: due Friday January 19 in Canvas at 10pm PST.
(Solutions will be available in Canvas under Files)

Labs

• Lab 8
• Lab 7
• Lab 6
• Lab 5
• Lab 4
• Lab 3
• Lab 2
• Lab 1

Course Resources

• Slides
• Lab Write-Ups
• Your Engineering Notebook
• Lab resource page
(includes directions for installing lab software on your Windows or Linux PC)
(software now available on ITS PCs as well)
• Lab policies (a must read!)
• Topic, homework and reading schedule
• Text: Fundamentals of Digital Logic with Verilog Design by Stephen Brown and Zvonko Vranesic.
  First or Second or Third Edition
  McGraw-Hill 2013. ISBN-13: 978-0073380544 or ISBN-10: 0073380547 (these are the ISBNs for the third edition)
  

  There are several options for acquiring the text:
  But make sure the version you get says Verilog and not VHDL.

  1. Buy a new or used version of any edition from ??? for ???
  2. Buy the custom version of the text (ISBN:9781308394329) from the UCSC bookstore for $107.50.
     This is a new softcover black and white version of the text with only the chapters that will be covered.
  3. Rent the e-book version of the custom text through the bookstore.
  4. Buy the e-book version of this text from McGraw-Hill.

Course Information

• Lecture: MWF 12:00-1:05pm Social Sciences 2 Rm 75
• Lab: Baskin Engineering 104.
  • Section 1 TuTh 9:50-11:40am
  • Section 2 TuTh 11:40-1:30pm
  • Section 3 TuTh 1:30-3:20pm
  • Section 4 TuTh 3:20-5:10pm
  You must attend at least the first meeting of your section each week and you will probably need to attend the second as well.
  You may work in the lab at other times (and you will need to!).
  Installing the Vivado Webpack on your windows or linux computer will make you less dependent on the lab. If you bring your laptop to the lab we can help you install it. If you have a Mac you can run Vivado by installing Windows using Bootcamp or a Virtual environment such as VMWare.
• LSS Small Group Sessions: Sign up at https://sserc.ucsc.edu/slug-success
  • Monday 4:15PM - 5:15PM in Jack's Lounge
  • Tuesday 10:30AM - 11:30AM in Jack's Lounge
  • Friday 10:45AM - 11:45AM in Jack's Lounge

• Staff:
• Instructor: Martine Schlag
  e-mail: martine followed by @soe.ucsc.edu
  Office Hours: Wednesday 10:00-1100am and Friday 2:00-3:00pm
  E2 219 (northwest corner), (831)459-3243
• TAs:
  • Joseph Grant e-mail: jdgrant followed by @ucsc.edu
  • Erik Jung e-mail: eajung followed by @ucsc.edu
• Lab Tutors:
  • Roger Berman e-mail: raberman followed by @ucsc.edu
  • Krystine Carrington e-mail: kmcarrin followed by @ucsc.edu
  • Anthony Koutroulis e-mail: aakoutro followed by @ucsc.edu
  • Hunter Coffman e-mail: hcoffman followed by @ucsc.edu
  • Olyad Kebede e-mail: okebede followed by @ucsc.edu
  • Thomas Nijssen e-mail: tnijssen followed by @ucsc.edu
  • Jason Ting e-mail: jting2 followed by @ucsc.edu

• MSI Learning Assistant:
  • Kai Huang e-mail: kaihuang followed by @ucsc.edu

• Grading
• Pre-requisite: CMPE12/L
• Requesting academic accommodations

Other Information

• Academic Integrity
• SOE home page
• FPGA FAQ
• Murphy's Law
• Unacceptable proof techniques
• Direction of current flow (the holes have it!)
• Pictures of MOS transistors (Scroll down to about the middle of the page)
• Lego Logic
• Off-topic but an example of a thorough report: An engineer's guide to cats

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