CMPE100
Logic Design

LAST QUARTER Click here for Spring 2007.

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Homework Assignments

• Homework 6: due Wednesday March 14, at the beginning of class (2:00pm).
• Homework 5: due Monday February 26, beginning of class (2:00pm).
• Homework 4: due Friday February 16, beginning of class (2:00pm).
• Homework 3: due Wednesday Janurary 31, beginning of class (2:00pm).
• Homework 2: due Wednesday January 24, beginning of class (2:00pm).
• Homework 1: due Wednesday January 17 beginning of class (2:00pm).

Labs

• Lab 8
• Lab 7
• Lab 6
• Lab 5
• Lab 4
• Lab 3
• Lab 2
• Lab 1

Course Resources

• Slides
• Lab Write-Ups
• Your Engineering Notebook
• Lab resource page
• Lab policies (a must read!)
• Text: Fundamentals of Digital Logic with Verilog Design by Stephen Brown and Zvonko Vranesic.
  McGraw-Hill 2003. ISBN 0-07-282315-1
  

Course Information

• Lecture: MWF 2:00-3:10pm Engineering 2 192
• Section: Monday 1-2pm in Baskin Engineering 104
• Lab: Baskin Engineering 104.
  • Section 1 TuTh 10:00-11:45
  • Section 2 TuTh 12:00-1:45
  You must attend at least the first meeting of your section each week and you will probably need to attend the second as well.
  You may work in the lab at other times (and you will need to), except for W 3:30-5:30pm and Th 3:30-5:30pm when other classes are held in the lab.
• Staff:
• Instructor: Martine Schlag
  E2 219 (northwest corner)
  martine@cse.ucsc.edu
  (831)459-3243
  Office Hours: Wednesday 9-10am and Friday 12-1pm

• TA: Anna Neal
  e-mail: aneal@soe.ucsc.edu

• TA: Laurel DeMarco
  e-mail: laurel@soe.ucsc.edu
  
• Grading
• Pre-requisite: CMPE12/L

The pre-requisite for CMPE100/L is CMPE12/L. Although it's not a formal pre-requisite, CMPE16 is advised.

• Requesting academic accommodations

Other Information

• Academic Integrity
• CS/CE home page
• FPGA FAQ
• Murphy's Law
• Unacceptable proof techniques
• Direction of current flow (the holes have it!)
• Pictures of MOS transistors (Scroll down to the about the middle of the page)
• Lego Logic

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