CMPE100/L
Logic Design

Welcome to the evolving 100 Home Page

Discussion: Piazza cmpe100/L forum ( to sign up for Piazza)

Homework Assignments

• Homework 6: due Friday June 7 in Canvas at 10pm PDT.
• Homework 5: due Wednesday May 22 in Canvas at 10pm PST.
• Homework 4: due Friday May 10 in Canvas at 10pm PST.
• Homework 3: due Wednesday April 24 in Canvas at 10pm PST.
• Homework 2: due Wednesday April 17 in Canvas at 10pm PST
• Homework 1: due Wednesday April 10 in Canvas at 10pm PST.
(Solutions will be available in Canvas under Files)

Labs

• Lab 8
  You must attend your Tuesday 6/4 section to get the parts kit for this lab.
  Bring your ID.
  Demo due: Thursday 6/6 end of your section
  Write-Up due: Thursday 6/13 11:55pm
  Last day to submit Write-Up: Friday 6/14 11:55pm
  (with late penalty)
• Lab 7
  Demo due: Thursday 5/30 end of your section
  Write-Up due: Sunday 6/9 11:55pm
  Last day to submit Write-Up: Wednesday 6/12 11:55pm
  (with late penalty)
• Lab 6
  Write-Up due: Sunday 5/26 11:55pm
• Lab 5
• Lab 4
• Lab 3
• Lab 2
• Lab 1

Course Resources

• Slides
• Lab Write-Ups
• Your Engineering Notebook
• Lab resource page
(includes directions for installing lab software on your Windows or Linux PC)
(software now available on ITS PCs as well)
• Lab policies (a must read!)
• Topic, homework and reading schedule
• Text: Fundamentals of Digital Logic with Verilog Design by Stephen Brown and Zvonko Vranesic.
  First or Second or Third Edition
  McGraw-Hill 2013. ISBN-13: 978-0073380544 or ISBN-10: 0073380547 (these are the ISBNs for the third edition)
  

  There are several options for acquiring the text:
  But make sure the version you get says Verilog and not VHDL.

  1. Buy a new or used version of any edition from ??? for ???
  2. Not sure yet if the bookstore is carrying it this quarter.
  3. Buy the custom version of the text (ISBN:9781308394329) from the UCSC bookstore for $107.50.
     This is a new softcover black and white version of the text with only the chapters that will be covered.
  4. Buy the e-book version of this text from McGraw-Hill.

Course Information

• Lecture: MWF 1:20-2:25pm Kresge 327
• Lab: Baskin Engineering 104.
  • Section 1A TuTh 9:50-11:40am
  • Section 1B TuTh 11:40-1:30pm
  • Section 1C TuTh 1:30-3:20pm
  • Section 1D TuTh 3:20-5:10pm
  You must attend at least the first meeting of your section each week and you will probably need to attend the second as well.
  You may work in the lab at other times (and you will need to!).
  Installing the Vivado Webpack on your windows or linux computer will make you less dependent on the lab. If you bring your laptop to the lab we can help you install it. If you have a Mac you can run Vivado by installing Windows using Bootcamp or a Virtual environment such as VMWare.

For LSS tutoring, sign up through Slug Success and Schedule an Appointment by clicking in the blue box at the top right of the screen.

• LSS Small Group Sessions:
  Sergio:
  • Monday 10:45-11:45am in Baskin 391
  • Tuesday: 7:15-8:15pmin Baskin 391
  • Thursday: 10:00-11:00amin Baskin 391
  Phu:
  • Monday 5:45pm - 6:45pm in Jack's Lounge
  • Tuesday 1:45pm - 2:45pm in Jack's Lounge
  • Wednesday 10:45am - 11:45am in Jack's Lounge

• Staff:
• Instructor: Martine Schlag
  e-mail: martine followed by @soe.ucsc.edu
  Office Hours: Tuesday 1-2pm and Friday 11:00am-noon
  E2 219 (northwest corner), (831)459-3243
• TAs:
  • Anthony Koutroulis e-mail: aakoutro followed by @ucsc.edu
  • Jason Ting e-mail: jting2 followed by @ucsc.edu
• Lab Tutors:
  • Michael Wai Chan e-mail: wakchan followed by @ucsc.edu
  • Anon Cheewakarn e-mail: acheewak followed by @ucsc.edu
  • Hunter Coffman e-mail: hcoffman followed by @ucsc.edu
  • Andy Kang e-mail: mykang followed by @ucsc.edu
  • Jeffrey Ng e-mail: jesang followed by @ucsc.edu
  • Thomas Nijssen e-mail: tnijssen followed by @ucsc.edu
  • Aditya Sehgal e-mail: adsehgal followed by @ucsc.edu

• SSI tutor:
  • Phu Le e-mail: phvle followed by @ucsc.edu
  • Sergio Mendez Vargo e-mail: smendezv followed by @ucsc.edu

• Grading
• Pre-requisite: CMPE12/L
• Requesting academic accommodations

Other Information

• Academic Integrity
• SOE home page
• FPGA FAQ
• Murphy's Law
• Unacceptable proof techniques
• Direction of current flow (the holes have it!)
• Pictures of MOS transistors (Scroll down to about the middle of the page)
• Lego Logic
• Off-topic but an example of a thorough report: An engineer's guide to cats

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