SOLUTIONS TO HOMEWORK #6:
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12.8

The MOVE instruction is NOT a TAL instr.. Hence, it would need to be
assembled into TAL instructions. Those TAL instructions would probably
involve register $1, thereby incorrectly overwriting it.

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12.10

If the exception handler returned control to a user program without
re-enabling interrupts, interrupts would be PERMANENTLY disabled.


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12.11

Yes, the exception handler could return control to a user program while
the processor is still in kernel mode. This could happen if the handler
is not written correctly.

This leaves a potential loophole for breach of computer secutiry. The
kernel would be exposed to the user, who can then do anything with the
system because he/she then has privileges that are otherwise only
available in the kernel mode.


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13.5

A few MAL and TAL instructions that do nothing (no-op) are:

	add	$0, $0, $0
	add	$0, $8, $20
	addi	$0, $0, 0
	move	$8, $8

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13.6

	li	$18, 200
	add	$20, $21, $18

The data dependency exists if the value in $18 is ndded (for the add
instruction) before it has been written (by the li instruction).
A pipeline with more than two stages would require a check to make sure
that data was available when needed. If data was not available, then
holes (or bubbles) would be introduced into the pipeline.

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Cache problem: A set-associative cache consits of 64 lines, or slots,
divided into 4-slot sets. Main-memory contains 4K blocks of 128 words
each. Show the format of main memory addresses. (This implies it is 4-way
set-associative cache. Total number of effective lines is 64/4=16, each
with 4 slots.) 

	Block size	= 128 words = 512 bytes = 2^9 bytes
	Mem size	= 4K * 128 words	= 2^21 bytes
	Cache size	= 64 blocks
			= 64 * 2^9 bytes	= 2^15 bytes

	We need 9-bits to address the 512 bytes bytes of each block

	The 16 lines of cache reuqire 4-bits to be addressed	

	The remaining bits = 21 - (9 + 4) = 8 make up the TAG.


	20		   13 12       9  8                    0
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	|	TAG	     |	 Line    |	block		|
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